A mixer circuit with a down-conversion mixing component for down-converting a radio frequency (RF) signal can be used in particular in an RF receiver.
For illustration, a block diagram of an exemplary analog direct conversion receiver 10 is presented as FIG. 1.
The depicted receiver 10 comprises a low noise amplifier (LNA) 11 for amplifying received RF signals, mixers 12 for down-converting the amplified RF signals, an analog signal processing component 13 for processing the down-converted signals, analog-to-digital converters (ADC) 14 for converting the processed analog signals into digital signals, and a digital signal processing component (DSP) 15 for a further processing of the digital signals. For processing the analog down-converted signal, the analog signal processing component 13 comprises an Nth-order low-pass filter (LPF), an analog gain control (AGC), a direct-current (DC) offset cancellation, etc. For processing the digital signal, the DSP 15 comprises a decimation stage, an LPF, etc. The output of the DSP 15 constitutes the digital baseband (BB) output.
The receiver 10 can be integrated for example in a mobile terminal 16 for receiving and processing RF signals transmitted by a mobile communication network.
FIG. 2 is a schematic circuit diagram of a straightforward implementation of the front end of the receiver of FIG. 1. The circuit of FIG. 2 comprises an RF amplifier 21 with the LNA 11, a Gilbert cell 22 as mixers 12, and two LPF stages 25, 27 as analog baseband filter of the analog signal processing component 13. Instead of the depicted second order LPF 25, 27, a higher order LPF can be used as well.
The LNA 11 comprises two input terminals and two output terminals. The LNA 11 amplifies received RF signals RF IN and outputs the amplified signals as voltages Urf+ and Urf−. The outputs terminals of the LNA 11 are connected to two signal input terminals of a down-conversion mixing component 23 of the Gilbert cell 22. The mixing component 23 receives via two additional input terminals alternating local oscillator signals LO+ and LO−, which enable a down-conversion of input radio frequency signals RF IN. The resulting baseband signals are output as voltages Ubb+ and Ubb− via a respective output terminal. The output of the mixing component 23 is moreover connected within the Gilbert cell 22 to a mixer load 24.
The first output terminal of the mixing component 23 is connected via a first input terminal of the first LPF stage 25 and a resistor R3a to a first input of an operational amplifier 26 of the first LPF stage 25, and a first output of operational amplifier 26 is connected to a first output terminal of the first LPF stage 25. A capacitor C1a on the one hand and a resistor R1a on the other hand are arranged in parallel to each other between the first input and the first output of the operational amplifier 26.
The second output terminal of the mixing component 22 is connected via a second input terminal of the first LPF stage 25 and a resistor R3b to a second input of the operational amplifier 26, and a second output of the operational amplifier 26 is connected to a second output terminal of the first LPF stage 25. A capacitor C1b on the one hand and a resistor R1b on the other hand are arranged in parallel to each other between the second input and the second output of the operational amplifier 26.
The first output terminal of the first LPF stage 25 is connected via a first input terminal of the second LPF stage 27 and a resistor R4a to a first input of an operational amplifier 28 of the second LPF stage 27, and a first output of the operational amplifier 28 is connected to a first output terminal of the second LPF stage 27. A capacitor C2a on the one hand and a resistor R2a on the other hand are arranged in parallel to each other between the first input and the first output of the operational amplifier 28.
The second output terminal of the first LPF stage 25 is connected via a second input terminal of the second LPF stage 27 and a resistor R4b to a second input of the operational amplifier 28, and a second output of the operational amplifier 28 is connected to a second output terminal of the second LPF stage 27. A capacitor C2b on the one hand and a resistor R2b on the other hand are arranged in parallel to each other between the first input and the first output of the operational amplifier 28.
The two LPF stages 25, 27 apply a second order low pass filtering on the baseband signals Ubb+ and Ubb− received from the Gilbert mixer 22. The resulting low-pass filtered baseband signals are forwarded to the analog-to-digital converters 14 of FIG. 1.
Implementing a receiver with such a direct conversion architecture has the advantage that it is cheaper than other conversion architectures, like super-heterodyne architectures, since expensive band pass filter components for an intermediate frequency (IF) are not required in a direct conversion.
It is further of advantage to realize a receiver as a system on chip (SoC) solution, that is, to implement the components of the receiver on a single chip. Cost, size and other reasons would make the use of the deep sub-micron Complementary Metal Oxide Semiconductor (CMOS) technology attractive for such an SoC solution.
When using a deep sub-micron CMOS implementation, however, the flicker noise, which is also referred to as 1/f noise as it is inversely proportional to the frequency, has to be taken into account. Flicker noise is especially a problem in second generation (2G) systems like the Global System for Mobile Communications (GSM) and, to a lesser extent, as well in third generation (3G) systems. The noise problem is increased with modem and future CMOS technologies which require a low supply voltage. As the supply voltage decreases, also the noise has to decrease. An additional difficulty with a lower supply voltage is the linearity. As the threshold and saturation voltages are consuming in the case of a low supply voltage a larger portion of the supply voltage range, the linearity is worse with lower supply voltages than with higher supply voltages. The conventional direct conversion receiver will therefore be increasingly difficult to implement in future low voltage processes.
An important component of a direct conversion receiver and the most critical one in terms of linearity and noise is the mixer. A conventional direct conversion receiver comprises a passive load for the mixer, which is composed of a resistor and a capacitor to provide a suitable signal gain and a first order attenuation for interferences. Such a passive mixer load is difficult to design for a desired gain, a desired noise and a desired linearity, as these factors are all linked together through the bias current of the mixing component and the load impedance. A conventional mixer structure will therefore have considerable noise and linearity problems in modern CMOS architectures operating with a low supply voltage.
The noise problems in a direct conversion receiver can be avoided by using a Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) based chip for the critical RF and baseband blocks.
Therefore, usually the digital baseband components of a direct conversion receiver, like the DSP, are implemented using CMOS technology. The RF components of a direct conversion receiver, including the LNA, the mixers and the analog baseband signaling processing component, in contrast, are usually implemented using BiCMOS technology or other analog-oriented semiconductor processes. Thus, a complete receiver is usually implemented using at least two separate chips for RF and digital baseband, which increases the production costs.